3D R&D and Collaboration

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Mitsubishi Throws its Hat in the 300mm Wafer Bonding Ring

By Francoise von Trapp On Jan. 18, 2012

Earlier this week, Mitsubishi Heavy Industries, Ltd. announced it had “developed the world's first fully automated 12-inch (300 millimeters) wafer bonding machine, capable of producing 3-dimensionally integrated LSI (large-scale integration) circuits at room temperature.” This tool is targeted to the MEMS, 3D LSI's, and the RF market. I was skeptical of the words “world’s first” when I know Read More>>

The Great 3D Supply Chain Debate: The Handoff

By Francoise von Trapp On Dec. 20, 2011

The supply chain business model for manufacturing 3D stacked ICS has caused perhaps one of the hottest debates so far in commercializing 3D semiconductor processes. It’s easy to see why. Beyond the rather obvious question of who will own the liability of damaged devices, there’s a good deal of revenue at stake for those who make the investment in adding capacity for middle end of the line (MEOL) Read More>>

Invensas and ALLVIA Collaboration Results in Full 3D R&D Line; Paves the Way for 3D Manufacturing

By Francoise von Trapp On Nov. 03, 2011

Earlier this week Invensas Corporation, a wholly-owned subsidiary of Tessera Technologies, Inc., announced both its acquisition of ALLVIA’s patent assets, and a two-year collaborative partnership with ALLVIA to further develop technology and intellectual property (IP) in the 3-dimensional integrated circuit (3D-IC) packaging space. This strategic alliance is expected to optimize the strengths of Read More>>

Perspectives on 3D Integration: The Researchers

By Francoise von Trapp On Oct. 13, 2011

To listen to John Lau, of ITRI, speak on the topic of 3D integration is to experience a passion for technology that rivals no other; except perhaps that of Rao Tummala of Georgia Tech. But John is definitely more vocal in his passion. Rao has a softer, gentler approach. At this year’s IWLPC in Santa Clara, both expressed their perspectives on what they see as the most cost effective and Read More>>

Georgia Tech's 3D Interposer Technologies Provide Low-cost 3D Option

By Q3D Notes On Aug. 22, 2011

At SEMICON West 2011, Prof. Rao Tummala of Georgia Tech presented the unique glass and silicon-based 3D Interposer technologies being developed at Georgia Tech, claimed to be simpler and cheaper than 3D ICs with TSV for many mobile and consumer applications at SemiconWest 2011. in his presentation, Tummala discussed the primary differences and challenges between traditional industry's approach to Read More>>

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CEA-Leti: The Mother Ship Re-visted

By Francoise von Trapp On Jul. 08, 2011

Last time I visited Leti on the Minatec Campus was in October 2009. Recently, when I was back for Leti’s Annual Research Reviews, Mark Scannell, head of the 3D integration program, took me on another tour. A lot has been going on here in the past 2 years. For one thing, the building I saw going up in its early stages has been completed. There’s now a showroom displaying all the nifty Read More>>

3D Integration Research, SEMATECH Style

By Francoise von Trapp On Nov. 21, 2010

SEMATECH’s story is one that is truly built upon the essence of collaboration. SEMATECH is not a traditional research center. Rather, it is a technology research consortium that exists to serve the best interests of its worldwide members and partners. Originally established in Austin, TX as an experiment in combining government and industry to further the development of semiconductor technologies, Read More>>

CEA-Leti: A visit to the mother ship

By Francoise von Trapp On Dec. 01, 2009

If your company is located in France, and/or is involved in micro and nanotechnologies for microelectronics, chances are it’s either a spin out of Leti, its parent organization CEA, or is closely tied in ongoing collaboration to this major European research center for applied electronics. At least that is the impression I came away with after visiting Leti at its Minatec campus in Grenoble, France, as well as four other companies (Alchimer, Soitec, Replisaurus/S.E.T. Read More>>

Replisaurus/SET: A Master Plan

By Francoise von Trapp On Nov. 09, 2009

It’s only fitting that Replisaurus’s equipment division, SET Smart Equipment Technology, which is located in Saint Jeoire, France, found its way into the Tour de France in 3D. After all, the town is on the route of the real Tour de France. Read More>>

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Forum Structure

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SEMICON West 2010 3D Wrap-up Forum (Discussions: 7)

Last Post: Re:3D Co-Design Challenges (concluded)
By Francoise von Trapp on Aug. 02, 2010

3D MEMS Forum (Discussions: 2)

Last Post: Re:MEMS and 3D IC integration:...
By Karen Lightman on Oct. 22, 2010

3D Packaging Forum (Discussions: 3)

Last Post: Re:Updates on Package on Packa... (concluded)
By Francoise von Trapp on Apr. 05, 2010

Open Forums (Discussions: 2)

Last Post: Re:Could moving forward with 4...
By Francoise von Trapp on Nov. 04, 2011

3D Processes Forum (Discussions: 1)

Last Post: Re:3D Stacking Methods for TSV... (concluded)
By Francoise von Trapp on May. 10, 2010

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SEMATECH to conduct rigorous manufacturability assessments to enable high volume manufacturing readiness of 3D technology

By Q3D Notes On Jan. 16, 2012

To enable high-volume production readiness of 3D-based products, SEMATECH’s 3D Interconnect and Manufacturability programs will be conducting Equipment Maturity Assessments (EMAs) of several critical 3D tools during 2012 to establish functional equipment capabilities and address high volume manufacturing maturity issues. The assessment is a cooperative effort among experts from SEMATECH’s 3D program, Read More>>

SEMATECH’S 3D ENABLEMENT CENTER FOCUSES ON ADDRESSING CHALLENGES FACING FUTURE HIGH VOLUME 3D APPLICATIONS

By Q3D Notes On Dec. 20, 2011

SEMATECH’s 3D Enablement Center (3D EC), together with the Semiconductor Industry Association (SIA) and Semiconductor Research Corporation (SRC), has identified the top technical challenges for new “killer” applications to enable future development of heterogeneous 3D integration beyond mobile wide I/O DRAM. Following the introduction of the wide I/O DRAM, further research and development of Read More>>

Rambus and ITRI Collaborate to Develop Interconnect and Advanced 3D Packaging Technologies

By Q3D Notes On Dec. 16, 2011

Rambus Inc, one of the world's premier technology licensing companies, announced today it is engaging with the Industrial Technology Research Institute (ITRI) in Taiwan, one of the world's leading research institutes, on the development of interconnect and 3D packaging technologies. In addition, Rambus has joined the Advanced Stacked-System Technology and Application Consortium (Ad-STAC), a multinational Read More>>

Si2 Announces Founding Members of the Open3D Technical Advisory Board

By Q3D Notes On Dec. 09, 2011

The Silicon Integration Initiative (Si2) announced today the founding members of their Open3D Technical Advisory Board (TAB), which is chartered to enable interoperable 2.5D and 3D design flows with open standards, providing common formats and interfaces. The founding members of the Open3D TAB are: ANSYS (ANSS), Atrenta, Cadence Design Systems (CDNS), Fraunhofer Institute, GLOBALFOUNDRIES, Intel (INTC), Read More>>

Honeywell and Tezzaron to Build Rad Hard 3D-ICs

By Q3D Notes On Dec. 09, 2011

Honeywell Microelectronics and Tezzaron Semiconductor are working together to produce a new range of radiation-hardened (rad hard) integrated circuits. Honeywell’s sturdy, well-qualified S150 processwill use Tezzaron’s 3D stacking to greatly increase circuit density without migrating to a smaller node. The resulting three-dimensional integrated circuits (3D-ICs)are also expected to use Read More>>

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