By Q3D Notes On Jul. 28, 2009
Last year, it was all about through silicon vias (TSVs), this year, it’s all about everything else needed to achieve 3D IC stacks using TSVs. I’m talking about 3D IC technology discussions at this year’s SEMICON West. A clear example of this was SUSS MicroTec’s workshop on wafer thinning and handling, held off site at the St. Regis Hotel on July 15. Read More>>
By Q3D Notes On Apr. 24, 2010
In this post written and submitted by John H. Lau, Electronics & Optoelectronics Laboratory, ITRI, the true inventor of the Through Silcon Via (TSV) is revealed. Read More>>
By Francoise von Trapp On Nov. 01, 2010
Attending last week’s TSV Seminar in Tokyo, hosted by Electronic Journal, posed a bit of a challenge as all but one presentation was in Japanese. However, thanks to the detailed diagrams and smatterings of English in the proceedings along with careful note taking by Tegal Corp.'s interpreter Yukumi Hayafune, I was able to summarize the main points of the event. But first, a word about the different Read More>>
By Francoise von Trapp On Dec. 07, 2009
Processes addressing the handling of ultra-thin wafers have been a hot topic ever since it became clear that they are vital to a multitude of semiconductor applications such as MEMS, compound semiconductors, LEDs, fan-out WLP, CMOS image sensors (CIS) and most recently, 3D IC using TSV interconnects. Read More>>
By Francoise von Trapp On Oct. 21, 2010
When a research institute is evaluating different options for technology partnerships, what tips the scales in favor of one supplier over another? In the case of the recently announced common lab agreement between Leti and SPP Technology Process Systems (SPTS) to further develop processes for high aspect ratio TSVs, it was a matter of finding the ideal mix of key elements that included an established Read More>>