By Francoise von Trapp On Oct. 14, 2010
Much of the manufacturing equipment, processes, modeling and simulation tools, and materials being investigated for 3D IC integration technologies were first developed for MEMS fabrication and packaging. This discussion will examine how advancement of MEMS manufacturing processes help further the advancement of 3D IC and vice-versa.  We will look at synergies in the supply chain and discuss how Read More>>
By Francoise von Trapp On Apr. 21, 2010
By design, MEMS devices are already 3D stuctures, so when we talk about 3D MEMS, we’re actually talking about the integration of ICs and multiple MEMS sensors in the third dimension to create advanced “smart” systems. Read More>>
By Francoise von Trapp On Apr. 28, 2010
When it comes to stacking 3D die stacking with TSV, there are 3 basic approaches being considered: chip-to-chip (C2C), Chip-to-Wafer(C2W) and Wafer-to-Wafer (W2W). The first of these to reach commercialization is C2C, but development continues in the other two areas in hopes of increased throughput and yield, thereby reducing cost. Read More>>
By Francoise von Trapp On Mar. 22, 2010
Panelists and Participants: Welcome to the 3D wafer-level packaging (3D WLP) discussion in this week’s 3D Packaging update forum. Please join in the discussion by logging in and posting your questions and comments here. Read More>>
By Francoise von Trapp On Jul. 16, 2010
There is still work being done to perfect various processes needed to manufacture TSVs that are reliable and cost effective. This discussion will focus on what was featured this year at SEMICON West to help iron out the kinks. Read More>>